The present invention relates in general to high-speed integrated circuits and more particularly to a method and circuitry for implementing overflow detection structures for high-speed first-in-first-out (FIFO) operations.
FIFOs are used in a variety of circuit applications. For example, a serializer may use a FIFO structure to address different system timing requirements. In such an application, the integrated circuit often employs an internal clock that may not be synchronized with an external clock used to supply data to the integrated circuit. A FIFO is used to transfer the data from the external clock regime to the internal clock regime. Typically, such a FIFO includes a number of registers that operate in response to a write pointer and a read pointer. An external clock controls the write pointer while an internal clock controls the read pointer. A problem arises when the read and write pointers collide, that is, when they attempt to read and write the same FIFO register at about the same time. This condition is commonly referred to as an overflow condition and can result from improper resetting of the FIFO pointers caused by, for example, glitches in the pointer generation circuits, drifting of the external clock phase, etc. During an overflow condition, the data read from the FIFO may be corrupted. FIFOs thus need some type of overflow detection mechanism to detect an overflow condition and avoid this faulty operation.
Conventionally, overflow detection has been implemented using combinatorial logic whereby the read and write pointers into the same FIFO register are gated together to flag an overflow signal. Specifically, the read and write signals are logically ANDed such that when a collision occurs, an overflow detection signal is asserted. These types of overflow detection suffer, however, from possible glitches and thus erroneous flagging of overflow. Data loss occurs when an overflow detector output is used to reset the FIFO and to separate the read and write pointers. While a FIFO register resets, it cannot accept new data. Thus, an erroneous overflow flagging can cause data loss.
There is thus a need for an improved method and circuitry for implementing high-speed FIFO and overflow detection structures.